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clo
实现时分秒的计数和校正实现时分秒的计数和校正(Realized and correction of minutes and seconds count)
- 2009-12-21 22:52:39下载
- 积分:1
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frequence1
基于FPGA的等精度数字频率计,包含FPGA和单片机通信程序,解释非常详细。经过调试成功。(FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.)
- 2020-10-30 20:29:56下载
- 积分:1
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vga
说明: 实现在屏幕上显示绿色和红色相间的水平条纹。其中,vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分:1
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WM8731_WM8731L
wm8731音频编解码芯片使用介绍,该手册里面对该芯片进行了详细的描述,对各个单元模块也进行了详细的阐述(the handbook of WM8721/WM8731L)
- 2010-05-20 10:47:30下载
- 积分:1
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UDP
用FPGA中的三速以太网来实现UDP通信,功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)
- 2013-03-08 18:27:38下载
- 积分:1
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Verilog
这是个关于verilog入门的文档,有同志对verilog感兴趣,可以下载此文档,以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)
- 2011-11-06 13:18:07下载
- 积分:1
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vga显示代码,里面有ise工程文件,是直接调过去的,大家下载下来吧...
vga显示代码,里面有ise工程文件,是直接调过去的,大家下载下来吧-vga display code, which has ise project file is transferred directly past, everyone download it
- 2022-11-14 00:10:04下载
- 积分:1
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kt1
基于FPGA的可控100进制可逆计数器,运行环境maxplus(Controlled 100 hex reversible counter FPGA-based operating environment maxplus)
- 2012-05-17 12:19:54下载
- 积分:1
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medianfilter
图像滤波中的中值滤波,有效滤除椒盐噪声,使用verilog语言编写(Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language)
- 2011-10-13 17:08:48下载
- 积分:1
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Hardware Description Language VHDL of the frequency counter program can be used...
硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.
- 2023-01-23 07:20:04下载
- 积分:1