用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。...

寄存器的VHDL源码.可能有点简单 新手大家间量 希望和大家学习-VHDL source register. May be a bit simple volume between novice you would like to learn

六层的电梯控制系统 用VHDL描述同时还附有系统仿真图形

用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL description.

简单的8个CPU，包含PDF文件。他们可以查看详细信息

xilinx 开发板程序，VGA控制显示-Xilinx development board procedures, VGA display control

4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.-4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modified version.

使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation

VerilogHDL教程，很详细全面的Verilog教程，循序渐进，由浅入深，十分好的学习资料(VerilogHDL tutorial, very detailed and comprehensive Verilog tutorial, step by step, progressive approach, a very good learning materials)

本演示使用VGA输出和DVD播放器播放视频和音频输入

本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)