用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。...

利用dsp builder设计的IIR滤波器，已经验证完全可以使用，只需要把其中系数改变。内含VHDL代码(Design IIR filters by dsp builder have been verified , just change the coffetions including VHDL code.)

说明：  激光测速研究，主要介绍多普勒激光测速知识(Laser velocimetry study introduces laser-Doppler velocimetry knowledge)

verilog编写的DAC2902程序，用于高速的数模转换(verilog language,using for DAC2902 digital analog converter)

说明：  LVDS De-serialization

1024点fft verilog hdl(1024-point fft verilog hdl)

这是一些小代码的集合 希望能对大家有所帮助(This is a collection of some small code for all of us hope to be helpful)

这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。(This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.)

有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)

基于sopc ep2c5开发板的液晶字符显示例程-Sopc ep2c5 development board based on liquid crystal character display routine