使用vhdl语言实现对led的控制，还有电路仿真

能实现数字钟中时间的显示，并可对小时，分钟，秒进行调整-Can realize the time digital clock display, and on the hours, minutes, seconds to adjust

VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.

通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。-To learn through this article, will enable us to design some simple logic circuits and systems. Soon we will be able to transition to the design of complex digital logic systems.

VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02

FPGA implementation of simple Multi-tone Electronic Keyboard using DE2-115 board with a PS/2 keyboard and speaker

huffman transform in vhdl language

FFT with fix point 2*N