登录
首页 » VHDL » simple eight CPU, containing PDF files. They can check details

simple eight CPU, containing PDF files. They can check details

于 2022-07-03 发布 文件大小:2.13 MB
0 168
下载积分: 2 下载次数: 1

代码说明:

简单的8个CPU,包含PDF文件。他们可以查看详细信息

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 8051IP nuclear source code
    8051IP 核源代码-8051IP nuclear source code
    2022-05-17 06:21:49下载
    积分:1
  • ozgul2013
    说明:  Digital pre-distortion (DPD) is an advanced digital signal-processing technique that mitigates the effects of power amplifier (PA) nonlinearity in wireless transmitters. DPD plays a key role in providing efficient radio digital front-end (DFE) solutions for 3G/4G basestations and beyond. Modern FPGAs are a promising target platform for the implementation of flexible wireless DFE solutions, including DPD.
    2019-01-05 18:20:30下载
    积分:1
  • histogram_new
    Verilog语言描述,统计图片的像素值直方图(Verilog,Pictures of the pixel value histogram statistics)
    2021-03-04 17:39:31下载
    积分:1
  • jj
    说明:  电子工程师学习的最好的学习资料,能够了解电子设计必学软件资料。建议珍藏,电子设计初学者必备(Electronic engineers to learn the best learning materials, to understand the electronic design will learn software data. Recommended collection, electronic design for beginners)
    2014-06-10 20:04:54下载
    积分:1
  • A " percentage of seconds, seconds, minutes," digital stopwatch timer c...
    一个具有“百分秒,秒,分”计时功能的数字跑表,可以实现一个小时以内的精确至百分之一秒的计时。 数字跑表的显示读者可以通过编写数码管显示程序来实现,本训练只给出数字跑表的实现过程。 读者还可以通过增加小时的计时功能,实现完整的跑表功能。-A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.
    2022-05-05 18:35:57下载
    积分:1
  • dds digital shift Signal Generator, full
    dds数字移相信号发生器,功能齐全通过验证-dds digital shift Signal Generator, full-featured validated
    2022-08-15 06:38:32下载
    积分:1
  • a cycle ruduandency code
    实现一个循环冗余码,是老师给的例子,别的同学已经验证-a cycle ruduandency code
    2023-04-27 23:30:03下载
    积分:1
  • 主要是通过Altera公司的Cuclone系列的FPGA
    主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据;-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data
    2023-06-17 01:00:03下载
    积分:1
  • GgmsskModulatM
    GMSK的调制解调,理理想信道,画出其功率谱。 (GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)
    2020-07-02 02:00:02下载
    积分:1
  • c51
    51数字钟带各种扩展年,月,日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)
    2012-11-09 08:41:02下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载