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A basic SDH transmission module STM
一个SDH中最基本传输模块STM-1的帧头检测器,verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming
- 2022-02-07 03:42:51下载
- 积分:1
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freq_meter
使用verilog写的频率计,可切换档位(Frequency counter using verilog write switch stalls)
- 2012-12-08 00:54:56下载
- 积分:1
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LED
说明: 一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)
- 2019-06-28 15:18:09下载
- 积分:1
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shuzishizhong
基于DE2-115开发板设计的一个数字钟,能进行正常的小时、分、秒计时功能,并分别由开发板上面的数码管显示秒(60s)、分(60min)、小时(24hours)的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)
- 2020-11-01 11:39:54下载
- 积分:1
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LMS filter
这是一个用结构化语言编写的25抽头LMS算法建模.VHDL加法器/减法器、乘法器、延迟元件的代码分别编写并用LMS代码实例化。
- 2022-02-10 10:42:31下载
- 积分:1
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mult3
this is the multiplier 3 module for the reed solomon encoder
- 2009-03-23 17:22:55下载
- 积分:1
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complete with verilog language development USB2.0 IP source code, including docu...
完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
- 2022-08-22 09:20:17下载
- 积分:1
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nco11000
实现输入一正弦波和噪声的叠加,介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)
- 2010-05-16 14:19:53下载
- 积分:1
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Convolutional code encoder and Viterbi decoding to achieve
卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
- 2022-01-28 03:11:57下载
- 积分:1
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24x24-booth
可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)
- 2011-06-09 17:59:26下载
- 积分:1