基于NiosⅡ的2 de2_tvproject

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)

ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)

利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware description language of the people to see!

说明：  8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)

USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code

FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)

给予MSP430F147的串口通讯程序,能帮助你了解MSP430系列单片机和串口通讯的基本方法-give MSP430F147 Serial communication process can help you understand the MSP430 MCU serial communications and the basic methods

thesis about design and implementation neural network using FPGA