基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用...

design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)

MAX2 EPLD 的测试程序, VHDL语言编写.-MAX2 EPLD testing code, VHDL language.

XAPP928,可以参考学习.里面包含了色温调整、GAMMA调整以及空间抖动增强灰度算法，这３个基本是现在平板显示设备常用的图像预处理算法。

说明：  fPGA中的竞争冒险现象的来源及其解决方法(FPGA in the source of the phenomenon of competitive risk-taking and their solutions)

FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考(FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design)

用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,

使用matlab实现cdma 系统的rake接收机，比较最大比合并，等增益合并和选择性合并接收算法的性能(脢 鹿 脫脙matlab脢渭脧脰cdma 脧渭脥 鲁 渭脛rake 陆 脫脢脮 禄煤 拢 卢 卤 脠 陆 脧 脳 卯)

使用verilog在fpga开发板实现流水灯，包括整个工程文件(This code is used for early learners to study verilog。)

用Hspice实现一个三输入异或门，并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)

一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。(This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.)