Verilog HDL

在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.

说明：  amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc(amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc)

FPGA开发,DE2开发板上实现,从SD卡读出MP3文件并播放,(即是开发一个简单的MP3播放器)(FPGA development, DE2 development board realize, from the SD card to read out and play MP3 files, (that is, the development of a simple MP3 player))

他延误用户inrandom经历过或基于竞争的MAC方案是无界;用户可能需要等待论坛很长一段时间，直到他/她发送一些数据的机会。在otherhand，通过根据一定的deterministicpattern，这被称为由梅西和马特仕协议序列调度所述数据分组，延迟的hardguarantee可以完成。

verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be

说明：  经典的雷鸟车灯控制电路设计，各大高校实验必做题目(Thunderbird classic light control circuit design, major colleges and universities must do experimental subjects)

原理图和程序，都已经调试好了！可以直接使用！

verilog 写的 电话计费器程序-verilog to write a telephone billing program

可以给VHDL初学者看的实例，全部经过验证(VHDL beginners can see examples of all the proven)

用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--