一种基于LUT的预失真方法。其中的一部分，有参考价值。

基于FPGA的7x7块交织器设计，程序分交织、解交织两部分，并在QUARTUS II 9.0 下仿真通过，内附模块详细端口说明及仿真分析文件。

用fpga实现VGA16色真彩的图片显示,且在AX301实验板上已经调试过(VGA16 achieve true color with fpga pictures show, and in the AX301 has been tuned breadboard)

彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

用vhdl写的-using VHDL write

这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

C51 verilog 源代码，可以在逻辑中实现51单片机功能-C51 verilog

system gen & accel dsp 培训资料-system gen & accel dsp

VHDL语言实现H.264的opencore，内涵说明文档、源码和文献等资料。 -VHDL language H.264 realize the opencore, meaning that documents, information such as source code and documentation.

XILINX中LWIP协议例子应用指南，有实际例子(Examples of applications in LWIP agreement XILINX Guide, a practical example)