VHDL,Flappy bird

说明：  USB主机和设备的verilog代码，实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)

FPGA based design and Implementation of Advanced Encryption Standard

说明：  this code works with spi and uart interfaces.

个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)

vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at the same time with a simple note!

说明：  Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers

说明：  FPGA PLL 分析，包括时序分析等等。。。。。。。。。(FPGA PLL Analysis)

非常好的SDRAM Controller 设计文档。工程必备-SDRAM Controller Design of a very good document. Works required

用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-

本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。 本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目 的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。(This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.)