Combined unit GPS clock synchronization detection unit merger GPS synchronized c...

数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim

4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)

FREEDEV数字应用开发板上的I2C总线IP核的verilog描述-FREEDEV digital application development board I2C bus IP core verilog description of

vhdl交通灯实验报告-VHDL traffic lights Experimental Report

使用verilog实现全数字16QAM调制器，载波频率1MHZ，数据比特流的速率为100Kbps,(the modulation of 16QAM based on FPGA)

采用quartus的数模转换模块，RTL电路图(DAC module, RTL circuit diagram)

在Quartus中，利用FPGA例化的存储器实现程序的BOOTLOADER的搬移(In Quartus, the use of FPGA case of memory to achieve the program' s move BOOTLOADER)

本代码主要功能是PPM解码，采用Verilog语言，通过移位寄存器和组合电路实现解码。(The main function of this code is PPM decoding.)