适用于满足I2C协议的flash读/写操作程序，只需要设置要读/写的字节数，就可以直接使用！...

这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240

在Altera_PFGA上实现POWERLINK从站设计,这是目前最好的的最具爱的实现方案，具有很实用的参考价值。文章介绍了实现方案和主要思路。

Computer Architecture Handbook on Verilog HDL

直接数字频率合成，可以直接输出所需要的波形-Direct digital synthesizer, you can direct output of the waveform required

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

说明：  stm32f103 usart 控制led灯(STM32F103 USART control LED)

VGA显示原理与VGA时序实现论文,详细介绍了VGA的原理 (Principle and VGA VGA display timing to achieve paper, detailing the principles VGA)

这是Verilog语言的if else 语句的优化，不同的写法，编译出来，结果会有很多不同。请大家自己斟酌。-see the Chinese

verilog实现计时器timer，可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)

根据软件无线电的思想，提出了一种新颖的数字信号处理算法，对QPSK信号的相位进行数字化处理，从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差，用数字锁相实现收发端载波的同步，在频偏较大的情况下，估算频偏的大小，自适应设置环路的带宽，实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台，并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点，符合未来通信技术发展的方向。(According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.)