二维高斯实现的Vhdl代码

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

xilinx提供的频率发生器的VHDL源码，可以运行在spartan3的学习开发板上。-xilinx the frequency generator VHDL source code, spartan3 can run in the learning development board.

FPGA部分源代码，关于dsp48的应用，从一本很好的书上下的

三层电梯的详细电路 Foundation版 包括强行开关门打断(Elevator control Foundation project)

AD转换的Matlab程序，将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率)，然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)

一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)

FPGA中实现的硬件UDP 协议 FPGA中实现的硬件UDP 协议

LCD SpartaN3E fpga vi

由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统-By avalen bus adapter i2c bus VHDL program can be applied to Nios Embedded Systems

说明：  文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)