Comparator for Quartus

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis

用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.

可以给VHDL初学者看的实例，全部经过验证(VHDL beginners can see examples of all the proven)

FPGA的存储器代码的VHDL,verilog描述及测试代码-FPGA memory code VHDL, verilog description and test code

基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)

本文介绍一种波导双模双带滤波器的设计方法。(This paper presents a new class of dual-mode dualband filters in which each polarization is dedicated to a selected band. The equivalent circuit is a parallel combination of two inline networks that represent each polarization. A transmission zero is generated between the two bands by properly adjusting the relative orientations of the input and output coupling apertures.)

关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)

vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的(vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on)

说明：  VHDL BASED DATA COMPRESSION

C语言写得FIR滤波器代码，简单实用，是学习滤波器设计的好材料，附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design )