Comparator for Quartus

基于FPGA的实现小数倍分频代码，广泛应用于数字通信中。-FPGA-based implementation of a small multiple of sub-frequency code, widely used in digital communications.

verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)

基于fpga的fskpsk信号产生器，可实现对1.2kHz和2.4kHz正弦波的采样-based on the fpga and fskpsk signal generator,can achieve sample to the 1.2kHz and 2.4kHz sin wave

能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)

DS18B20温度测量程序 之后用于在LCD显示屏上显示对应的温度(DS18B20 test code)

基于Verilog的八层电梯设计，能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.

designing of 16 bit adder using 4 bit adder using verilog code

Meyers wavelet. DWT VHDL.

红外接收处理，根据外部波形记录波形的高低电平时间，从而得到波形数据。(Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.)