硬件描述语言,verilog HDL,实现了解码器的设计

vhdl寄存/计数器设计-VHDL Storage/counter design

自动计算fir滤波器系数的工具，不妨一试(Automatic calculation of filter coefficients fir tools, try)

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)

基于CPLD的签到器的设计，用三维数组队人名进行储存-Based on the attendance CPLD design, a few team names with three-dimensional storage

Program to implement convolution through VHDL-Program to implement convolution through VHDL...

papers based on distributed arithmetic.

用VHDL语言实现8-3线编码器，16-4线编码器-VHDL language used to achieve 8-3 line encoder ,16-4-wire encoder

讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form )

设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))

matlab code for communication