这是介绍嵌入式开发相关的资料。有总线与内存的操作

主要讲述了数码相机MIPI接口协议说明，工作模式及信号传输原理等(Camera Interface Overview)

vhdl code for counterand detemines how counter works

该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

vhdl random numbergenerater

LTE is an abbreviation for Long Term Evolution.

time to digital convertor

基于DE2开发板的VGA显示模块，仅供大家参考(DE2 development board based on the VGA display module, for your reference)