基于sopc ep2c5开发板的时间标记服务例程

60进制计数器,（由一六进制和十进制连线组成）(60 binary counter (hexadecimal and decimal by a connection form))

此代码是加密实现在 vhdl。在加密、 RC6 (Rivest Cipher 6) 是一种对称密钥 块密码从RC5派生。它是由Ron Rivest、马特 Robshaw、 雷西德尼和益群丽莎贤以满足高级加密标准(AES)竞争的要求设计的。该算法是一个五个入围者，和也提交给湖怪兽和CRYPTREC项目。它是一种专有

60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated

/功 能：1.实现与CPLD的通信,从而控制PWM的占空比. 2.实现LCD显示相关信息. // 3.实现对键盘按键的判断和确定相应的操作. 4.实现对电压电流的检测. // 5.实现过载保护功能,电流过大时,切断PWM输出,当排除过流故障后,自动恢复供电 // 6.实现用PID算法跟踪电压,实现稳压输出(/ Function: 1. Achieve communication with the CPLD to control the PWM duty cycle. 2 LCD Display relevant information.// 3. Realize the keyboard keys judgment and determine the appropriate action. 4. Achieve the voltage and current Detection// 5. achieve overload protection, current is too large, cut off the PWM output, when excluding overcurrent fault, automatically restore power// 6. achieve tracking voltage with PID algorithm to achieve the regulated output)

这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合与与仿真，并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测，同时还能实现其它的图像模块化处理算法，例如高斯滤波，平滑等。 (This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)

说明：  FPGA实现Jpeg压缩，和视频采集程序(Zynq - Main - register access Mio)

dsp与fpga通信的verilog程序，强烈推荐欢迎参考(dsp and fpga verilog communication program, it is strongly recommended to welcome reference)

verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~

七段数码管显示数字时 使用VHDL语言编写(VHDL The seven-segment LED display digital clock)

verilog实现的“状态机实现AD574数模转换”-verilog to achieve a " state machine to achieve AD574 digital-analog conversion"