本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。...

如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量-the hdl code of 8051 core

In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.)

完整的TPC编译码VHDL程序，直接就可以运行(TPC encoder and decoder)

statemachine project for my school

世界时钟，最简单的vhdl的fpga设计，是vhdl语言的入门级，jigon供参考娱乐

SMbus通讯协议的Verilog程序段，已通过Moldesim的仿真，可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)

用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。-failed to translate

Verilog实现DDS线性调频，Verilog实现DDS线性调频(Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM)