vhdl,双向移位寄存器，实现置数，左移及右移操作

说明：  点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

VHDL硬件描述语言与数字逻辑电路设计―― VHDL语言的基本知识和设计逻辑电路的基本方法及NAX的使用-VHDL hardware description language and digital logic circuit design

hilbert 变换的vhdl源代码，来源于网上，本人也做过简单的8抽头的，但这个的算法还没搞懂，希望懂行的下载了研究一下，给个中文的简单的说明！(hilbert transform VHDL source code from the Internet, I have been a simple 8-tap, but even before they get to know this algorithm, I hope knowledgeable downloaded to look for a simple description of the Chinese!)

这是一个AMBA APB桥实现VHDL。这包括主人，奴隶和试验台试验桥。我已经测试功能。

8位加减器，八位减法器与加法器，用过一个控制端可以自由变换，采用移位加法方式，用途广泛，利用减法位补码加法的理论实现。(8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition theory to achieve.)

FPGA驱动VGA接口显示字符 -FPGA-driven interface VGA display characters

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对4x4键盘的输入控制，并显示在一个8段式数码管上。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 the development board to realize 4x4 keyboard input control, and displayed in an eight-stage digital pipe.

详细说明：基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序，EccErrLoc文件夹为ECC错误定位程序。

2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)