vhdl,双向移位寄存器，实现置数，左移及右移操作

VHDL examples for counter design, use QuickLogic eclips

I2C端口的FPGA实现，网上较多，但发现不少有问题，这个是在网上代码的基础上修改过，验证可行。-I2C port FPGA, online more, but found that many problems This is a code on the Internet on the basis of the revised test feasible.

电梯的设计・用来控制6层的电梯设计原来・VHDL语言-Elevator designed to control the lift design 6 original VHDL language

VHDL数字系统设计和工程实践5，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice 4, including the principles, truth table and schematic, as well as VHDL source code.

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

矩阵求逆模块硬件实现,用verilog语言，基于ISE开发环境(implement of inverse matrix)

介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。(It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.)

ip core of the transceiver gtx

基于ISP的交通灯设计，实现了各路状态转换、警察控制、行人请求功能。(ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.)