一个用vhdl硬件描述语言实现的一个比较简单的除法器

说明：  小波变换的开源代码（Verilog HDL）包括有测试文件，本人看过，挺好。(code of dwt)

是一个LED点阵显示屏的原理图，非常详细，适合开发者学习(LED dot matrix display is a schematic diagram is very detailed, for developers to learn)

说明：  基于FPGA的液晶显示控制器的设计，FPGA用的是EP2C5,LCD用的是ST7920内核的122*32点阵的LCD，显示中西文字符(FPGA-based LCD display controller design, FPGA is used EP2C5, LCD is used in the ST7920 core of 122* 32 dot matrix LCD, display of Chinese and Western characters)

基于FPGA的数字系统设计,包含原理、工程应用和案例。(FPGA-based digital system design, including theory, engineering applications and cases.)

能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)

一个用VHDL设计的DDS信号发生器，包括两个pics的仿真结果。

xilinx 开发板原程序，双口RAM控制-Xilinx development board the original procedures, dual-port RAM control

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.

产生SH,SP,RS,SP,φ1,φ2驱动脉冲，用于驱动TCD1501的的源代码(To generate SH, SP, RS, SP, φ1, φ2 drive pulse for driving TCD1501 source code)