Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL...

用verilog语言编写的串口读写程序，波特率可调，亲测可用。(this is a program for UART by verilog, which is useful.)

说明：  FPGA接收串口UART发来的指令设定温度报警值，实时采集DS18B20温度传感器并显示，带报警功能(FPGA receives the instruction from UART, sets the temperature alarm value, collects and displays DS18B20 temperature sensor in real time, with alarm function)

Syplify经典英文教程。内含众多实验例程，Lab 1 Basic Synplify Run；Lab 2 Analyzing Critical Path and Assigning Timing；Lab 3 FSM (Finite State Machine) Compiler Constraints and Attributes(Syplify classic English tutorial. Contains numerous experiments routine, you can help learners to quickly grasp Syplify tips, is a rare foreign experiments tutorial.)

AES 128 bit with various device interface on FPGA

C语言写得FIR滤波器代码，简单实用，是学习滤波器设计的好材料，附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design )

VHDL开发环境，电梯控制系统，实现电梯的上下传送控制。-VHDL development environment, elevator control system, transmission control up and down elevators.

使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。(The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..)

UVM 1.2 golden code, (code for UVM, )

A VHDL source code for testing the digits and the switches on a spartan 3 basys board

一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing