Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL...

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis

矩阵键盘控制的FPGA，verilog语言实现，包括rtl，ucf,以及testbench的详尽代码(Exhaustive code matrix keyboard control FPGA, Verilog language, including the rtl, ucf, and testbench)

基于 hdl语言的re232通信实验的设计，程序简单明了，一学就会(rs232 communication)

通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)

NIOS II IDE 编程， FLASH测试程序，仅供参考。-NIOS II programming IDE, FLASH testing procedures, for information purposes only.

可直接用于zedboard上的串口通信，利用zynq7000的pl部分实现一个简单的UART串口通信(Can be used directly on the zedboard serial communication, the use of zynq7000 PL part of the realization of a simple UART serial communication)

说明：  基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)

verilog写的数字频率计的选择模块,用与显示的选择-written in Verilog digital frequency meter option module, used and display options

说明：  vhdl常见小实验代码，包括二进制比较器，4选1,8421十进制，8421转化成格雷码，8421余三码，分频器，数据码译码器，二进制减计数器，四位环形计数器等(VHDL common small experiment code)

8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages