Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL...

axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)

CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)

应用背景****************************************************************************关键技术这个项目的目的是研究开发板的最大。该项目是实现闪烁的发光二极管具有不同的频率和/关闭时，你按按钮。

一个很好的VHDL实现的功能模块程序,希望你可以用的上!-a good VHDL functional module procedures in the hope that you can use!

LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)

实现PWM波型....使用VHDL语言-Realization of PWM waveform using the VHDL language ....

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

xilinx CTC IPcore 误码率测试-xilinx CTC IPcore Bit Error Rate Test

有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.

least mean square algo implemented on verilog