数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84...

LCD12864的显示程序，使用的是verilog语言编写的显示程序，为PDF文档(LCD12864 display program, using Verilog language display program, as a PDF document)

FPGA使用串口实现字节拼接传输更大的数据，通过修改代码可以实现任意字节的拼接，并通过自己设定通信协议可以实现与STM32的通信，达到简单而又高效率的通讯效果

本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.

《VHDL程序设计教程》光盘使用说明 本光盘是邢建平和曾繁太所著《VHDL程序设计教程》一书的配书光盘。本光盘的著作权归作者所有。 清华大学出版社享有该光盘的中文简体版专有出版权。 本光盘包括如下目录： “e_teaching_vhdl”--CAI教学材料 包含全套的PowerPoint文件，可以直接用于教学，具体请参见该目录中的index.pps文件说明。 共包含前言、第一章到第六章的教学文件。目前包含的为中文版辅助材料。 “vhdl fortextboot”--教程代码 包含本书教程例子的所有代码。 “vhdl for lab”--教程实验部分代码 包含本书教程实验部分所有代码。 “vhdl solutions”--教程习题参考解答 包含本书教程习题参考解答的文档。 “class music”--课间休息音乐欣赏 包含课间休息的中外音乐欣赏。 ("VHDL Programming Guide" CD-ROM for use This disc is too SENSORS and Tseng Fan book "VHDL Programming Guide," a book with the book CD. Of the copyright of the CD-ROM of all. Tsinghua University Press entitled The Simplified Chinese version of the CD exclusive copyright. This CD includes the following directories: "E_teaching_vhdl"- CAI teaching materials Contains the full set of PowerPoint files can be directly used in teaching, specifically refer to the directory index.pps documentation. Contains a total of introduction, the first chapter to the sixth chapter of the teaching file. Currently contained in the supplementary material for the Chinese version. "Vhdl fortextboot"- Tutorial code Tutorial examples include all of the code book. "Vhdl for lab"- Tutorial test sections of code Experimental part of the tutorial contains all the code book. "Vhdl solutions"- solutions for reference Tutorial exercises Reference bo)

当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter

使用ALTERA上DE2平台，使用Verilog描述，交通灯控制。-Using ALTERA on DE2 platform, use the Verilog description of the traffic light control.

利用两个半加器来组成的全加器，是简单的vhdl语言入门-The use of two and a half adder to form the full adder is a simple entry-vhdl language

基于fpga状态机的交通灯设计，亮灯时间自己修改，程序简单易懂。(Traffic light design based on FPGA state machine, light time self-modifying, the program is simple and easy to understand.)

国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。(Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.)

基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列 -Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence