0到255任意整数半整数分频Verilog HDL.rar

GE PCI5565 PMC5565 PCIE5565反射内存网数据中断接收程序 接收中断 反射内存网 VMIC5565反射内存卡 实时仿真技术 PCI5565PIORC-110000(GE PCI5565 PMC5565 PCIE5565 reflective memory network data interrupt transmission program VMIC5565 reflective memory card real-time simulation technology)

FFT with FIR created by students in univercity

主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly

VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!

Once the FPGA is located, the rest of the mapping data for the other components can be determined dynamically its section mapping registers.

这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用，大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)

开关数据加载到寄存器并显示的设计与实现.3． 设计一个可以把4个开关的内容存储到一个4位寄存器的电路，并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse， 用btn[0]作为输入；8位寄存器模块，用btn[1]作为加载信号；7段显示管上的显示模块x7segbc；分频模块clkdiv，用以产生模块clock_pulse和x7segbc的clk190时钟信号。(Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the register in the sixteen decimal digital display tube. We used to go to the jitter module clock_pulse, with btn[0] as the input 8 bit register module, as the loading signal by btn[1] 7 segment display module on the x7segbc pipe frequency module clkdiv, clk190 clock signal for generating module clock_pulse and x7segbc.)

采用SG3525实现感应加热电源的频率跟踪。(SG3525 is used to realize frequency tracking of induction heating power supply.)

卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve

8位crc的verilog设计 通过仿真综合验证并已应用在工程里面 (verilog of 8bit error checkout )