these files are written in verilog but i am uploading in text format

频率计，vhdl语言， ispDesignEXPERT-Frequency meter, vhdl language, ispDesignEXPERT

用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)

64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。(64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.)

Verilog语法教程，适合初学者，详细(Verilog instruction book)

说明：  DDS VHDL include everything of dds AD9914

verilog code for apb to ahb convert

PCI Arbitor by VHDL -PCI Arbitor by VHDL

说明：  可调矩阵，最大32*32位浮点数乘法矩阵及仿真。(32*32 floating multiplication matrix)

说明：  FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变(FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping)

bch 编码和译码，用硬件语言vhdl实现(bch edcode and decoder)