电子密码锁的vhdl编程实现，不知以前有没有人做过的。

说明：  用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能(for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on)

this project is about FIR FIlter By VHdl codes in the ISE.

网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。(a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong. tested.)

this is a verilog code of true random number generator using butterfly puf

这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design

verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support

简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

MATLAB辅助设计数字滤波器源代码，QUATUS II 实现！(MATLAB-aided design of digital filter source code, QUATUS II implementation!)

VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!