SPI接口的vhdl代码，可以实现与单片机的spi通信，完整的工程

上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)

频移键控FSK的Verilog实现，带测试文件，并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)

本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。 本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目 的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。(This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.)

本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.

电子设计自动化中关于交通信号的转换的实现程序，基于VHDL语言实现的-Electronic design automation in the conversion of traffic signals on the realization of the procedure, based on the realization of VHDL language

该模块采用cordic算法计算正弦和余弦，并采用参数化方式实现。 ；包中存在其他模块。

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.

异步FIFO的实现，很经典的三段式状态机的写法。(The realization of the asynchronous FIFO, very classic three-step writing state machine.)

使用并行结构对32位数据进行前导零检测，使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)

vhdl code for multiplexer and detemines how multiplexer works