asynchronous reset state machine

该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)

采用VHDL编写的频率计，模块划分清晰易懂，基本原理为检测一个闸门脉冲周期内的信号次数，采用四段数码管显示

RS编码器在fpga上的实现，用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)

说明：  实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)

VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!

是51单片机常用头文件定义，直接调用就可以，包括：1602液晶，12864液晶，5110屏，I2C,UART,精确延时函数，PWM调速，DS1302，DS18B20,,,,,,,(51 microcontroller used header file defines direct call can include: 1602 LCD, 12864 LCD, 5110 screen, I2C, UART, precision delay function PWM speed control, DS1302, DS18B20,,,,,)

Verilog 实验代码。。。经典的，里面都是完整的项目文件。 ISE环境。(Verilog test code. . . Classic, which is a complete project file. ISE environment.)

说明：  先用Matlab理论仿真，再用Verilog语言在ISE环境下编写程序，可通过手机发送指令来控制上下变频器的参数。(Firstly, we use the theory of MATLAB to simulate, and then use Verilog language to write programs in ISE environment. The parameters of up-down converter can be controlled by sending instructions from mobile phone.)

这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction

说明：  通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)