Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考....

An odd parity checker as an FSM using VHDL

OFDM_TX_CR802.11-master 802.11协议 ofdm开发(OFDM_TX_CR802.11-master)

I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source

FFT处理器的FPGA设计方法，适合做信号处理的技术人员参考，用FPGA实现-FFT processor, FPGA design, suitable for signal processing technology for reference, using FPGA to achieve

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

对PCM编码的多路复用与解复用程序，VerilogHDL源程序-Of PCM-encoded multiplexing and demultiplexing process, VerilogHDL source

AHB to Wishbone memory interface VHDL source code

简易双口ram，使用两个ram ip core，一个写的同时另一个读，并且包含按键使能和数码管以及流水灯显示(Simple dual-port ram, two ram the ip core, a write while another read, and contains buttons to enable digital pipe and the water light show)

数字电路课程设计，用VHDL实现交通灯的控制(Digital circuit design using VHDL control of traffic lights)