Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考....

altera remote updata cyclone5 平台例程，无nios核版本(altera remote updata cyclone5 platform routine do not use nios)

这是用verilog语言实现的1024点ff程序t-This is achieved using Verilog 1024 language ff procedures point t

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.

cpu微命令vhdl源代码-cpu-order VHDL source code

位同步例程源代码,FPGA应用领域，Verilog-Bit synchronization routines source code, FPGA applications, Verilog

说明：  STM32F103 ADC 通过DMA进行读取(STM32F103 ADC reads by DMA)

根据按键控制状态机状态转换，内含仿真波形文件

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

实现basys3板子的串口通信，内容非常纤细，还带有数码管显示(Realization of serial communication of basys3 board)

利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))