sdram controller vhdl

VHDL写的8051内核,可用的,好用,有兴趣可下载,在外国网站下载的-write VHDL 8051 kernel, available, convenient, can be downloaded interested in the foreign website

Verilog 下 16位除法算法程序，高精度，固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles

vhdl code for carry lookahead addder

分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.

Browser modularization processing, browser modularization combing, browser modularization expansion

Vhdl code for aarithmetic logic unit

正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

CPFSK Demodulation Techniques

使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)