登录
首页 » VHDL » sdram controller vhdl

sdram controller vhdl

于 2022-03-11 发布 文件大小:14.83 kB
0 139
下载积分: 2 下载次数: 1

代码说明:

sdram controller vhdl

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • verlog hdl brushless motor control procedures have been in ModelSim Simulation
    verlog hdl无刷电机控制程序,已在modelsim仿真-verlog hdl brushless motor control procedures have been in ModelSim Simulation
    2022-03-25 00:10:35下载
    积分:1
  • VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。...
    VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。-VHDL development environment, taxi billing system to achieve the initial 10 yuan for each additional mile, automatic up 2.
    2022-03-26 01:55:17下载
    积分:1
  • verilog
    基于QUATEUS2的设计一个8位频率计verilog语言编程(The design is based QUATEUS2 an 8-bit frequency counter verilog programming language)
    2011-12-01 20:19:48下载
    积分:1
  • dianzhen
    如果需要用verilog设计一项比较简单的功能,那么这个浅显易懂的程序能让你很快明白点阵的设计方法,尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)
    2014-01-16 16:13:53下载
    积分:1
  • VHDL实现led灯的动态扫描,主要对CLK进行分频
    VHDL实现led灯的动态扫描,主要对CLK进行分频-VHDL realization led lamp dynamic scan, the main points of the CLK to the frequency
    2023-03-21 08:35:04下载
    积分:1
  • FPGA based implementation of a SDR
    FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
    2022-12-18 09:05:03下载
    积分:1
  • VHDL_COUNTING 000_255 LCD DISPLAY ( ĐẾM 000 ĐẾN 255 HIỂN THỊ LCD BẰNG NGÔN NGỮ VHDL)
    VHDL_COUNTING 000_255 液晶显示器 (ĐẾM 000 ĐẾN 255 HIỂN THỊ 液晶电视 BẰNG NGÔN NGỮ VHDL)
    2022-03-13 13:37:51下载
    积分:1
  • 循环码的verilog编码程序
    (7,4)循环码的verilog编码程序,(7,4)循环码的verilog译码程序((7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure)
    2020-06-27 02:00:02下载
    积分:1
  • FPGA2-DSP2-EDMA
    例程是基于quartus的,FPGA通过EMIF给DSP发送数据,里面包含了一个简单的状态机和一个基于IP核的fifo,适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)
    2020-12-04 16:09:24下载
    积分:1
  • 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (mo...
    一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
    2022-08-21 18:15:23下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载