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fir4btp
4tap FIR filter in verilog code
- 2014-01-13 22:30:58下载
- 积分:1
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计数器的VHDL语言程序实现1
VHDL语言编写的计数器程序,实现1到9999计数,并动态扫描显示,带清零和暂停功能,课上作业自编程序-VHDL language of the counter program to achieve 1-9999 counts, and the dynamic scan showed, with Clear and suspension of functions, classes, on a self-compiled programs
- 2022-01-21 03:16:50下载
- 积分:1
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DDR2 控制器
下载自opencore网站!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- 2022-08-10 04:02:14下载
- 积分:1
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DC motor controller is excellent VHDL source code can be sown in simulation tool...
直流电机控制器,属于精品vhdl源码,可在eda仿真工具上仿真实现-DC motor controller is excellent VHDL source code can be sown in simulation tools Simulation
- 2022-09-13 06:40:03下载
- 积分:1
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ASIC_LIB
ASIC设计中常用的运算模块,如加减,常系数乘法,截断,饱和等。(some modules used in ASIC design.)
- 2010-03-10 15:52:28下载
- 积分:1
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Taxi-automatic-billing
出租车自动计费系统的verilog程序代码(Taxi automated billing system verilog code)
- 2009-10-08 10:07:15下载
- 积分:1
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chaotic_1d
说明: 一维超混沌随机数的生成verilg,还有testbench仿真激励,modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)
- 2020-05-11 12:45:42下载
- 积分:1
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PIC单片机学习软件及其资料
说明: PIC单片机学习软件及其资料,入门到精通(PIC MCU learning software and its information, entry to proficiency)
- 2019-07-04 17:17:40下载
- 积分:1
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Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。...
Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。-Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.
- 2022-05-10 23:14:10下载
- 积分:1
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09image_generation
code qui affiche une image sur ecran vga
- 2013-05-09 21:21:10下载
- 积分:1