sdram controller vhdl

开关电源中用单片机产生可调电压控制PWM波程序,ADC0832读取输出电压(Single-chip switching power supply using adjustable voltage control PWM wave generation process, ADC0832 read the output voltage)

基本交通系统,实现城市交通路口的模拟仿真，自己的课程设计作品(Basic transport system, urban traffic junction simulation, design their own courses)

EDA技术及其应用《序列信号发生器的设计》，包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)

交织和解交织模块，采用矩阵交织方式，且有两套并行存储器，可以实现连续数据流操作，不会有数据滞留和丢失-Intertwined intertwined reconciliation module, interwoven matrix approach, and has two sets of parallel memory, you can realize continuous data stream operations, will not have data retention and loss

Laurent程序,用于CPM信号的调制,接收和分解,译码,以及判断(Laurent procedures for CPM modulation of the signal, and decomposition receiving, decoding, and to determine)

full adder in vhdl of 4 bits

wiley2007年的新书高级FPGA设计作者是权威的设计咨询公司老总，经验之谈-wiley2007-year senior FPGA design book author is the authority of the design consulting firm CEOs, experiences

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

基于Verilog的PCI总线接口的设计及应用-Verilog-based PCI-bus interface design and application.

68013与FPGA的通信，包含了固件程序与verilog程序(68013 and FPGA communication, including firmware and verilog program)