FSK调制通信系统的程序，比较实用，包括有限..

说明：  用FPGA实现8点fft，整个代码使用verilog编写，主要运用了加法器和乘法器，简单易懂(8-point FFT with FPGA, The whole code is written by Verilog, mainly using adder and multiplier, which is easy to understand)

电机控制中PWM波产生的程序，VHDL语言实现-Motor Control PWM wave generated by the procedure, VHDL language

说明：  FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)

FPGA 设计的四种常用思想与技巧-FPGA design ideas and techniques used in four

VHDL实现简单打地鼠游戏机，北邮数电实验(VHDL simple playing hamster games, BUPT number of electric experiment)

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

VHDL examples for 16x16 times, if need detail pls let me know

这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)

讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form )