关于基数分频技巧设计,基于VHDL语言,对实际设计有帮助

VGA 640x480 driver in verilog

基于cycloneIIFPGA芯片Ep2c5t144c8的解调程序，用VHDL语言生成-CycloneIIFPGA chip-based demodulation Ep2c5t144c8 procedures, using VHDL language generation

五级流水线CPU实现（带Hazard），还没来得及实现Cache求高人指教(pipeline CPU with Hazard)

verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

DE2将连接到LCD布局上，为Terasic off技术公司附上系统代码

完成cmos摄像头对图像的捕捉，然后进行拼接通过USB进行传输。(complete picture capture)

BCH3.c,提供m<21以下的所有码长的BCH编解码模块。以供大家参考。谢谢(BCH encoder&decoder GF(2^m) m<21)

least mean square algo implemented on verilog

高精度小数除法器设计与实现。 在FPGA开发板上实现小数除法器，输入输出信号N_in [15:0], D_in[15:0]，N_in[15:0]小于D_in，即被除数小于除数，输出商Q_out[15:0]中Q[15]一定为0，Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)

verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^