96x96数字复用/解复用SPI

60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated

帧同步的VHDL程序源代码，巴克码同步实现。(Frame synchronization of the VHDL source code, Barker code synchronization)

该模块实现一个寄存器堆的操作，其中前16个仅主机能写，规给为32-bit×32。后16个仅Micorblaze能写。读取没有限制。如果双方同时对同一地址进行读写操作，读回的数将是全1。(This module implement a register file of the operation, of which the first host 16 is only able to write rules to the 32-bit × 32. Micorblaze only 16 after the write. There is no limit to read. If the two sides at the same time to read and write operations to the same address, read back would have been a full one.)

NiosII的C代码,包括网卡,lcd,usb,串口,按键.(NiosII C code, including network cards, lcd, usb, serial, key.)

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language

verilog数字系统设计，一本很好的verilog学习的书籍，很适合初学者(verilog digital system design, a good verilog learning books, it is suitable for beginners)

EP2C5核心电路原理图，包括protel文件及其相应封装库-EP2C5 Core circuit Sch

利用FPGA开发软件 进行rs编码的仿真 模拟RS编码的过程步骤(rs code in FPGA)

说明：  LDPC码的FPGA实现，用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)

文件名：lcd1602lib.h 内　容：1602液晶的控制端口、数据端口和相关操作(The file name: lcd1602lib. H * inside let: 1602 LCD control port, data port and related operations )