用于压缩感知。OMP 是一种算法

用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)

Token Bucket Filter queue.

基于DDS的BPSK调制器设计Verilog源码( U57FA u4E8.08 u868)

usb控制器，有VHDL实现的，还有C++的源码，可以编译-usb controller, there is the realization of VHDL, as well as C++ source code can be compiled

说明：  led blinking program.................

可编程逻辑器件cpld与单片机双向通信的源程序-Programmable logic device CPLD and MCU for two-way communication of the source

使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

说明：  并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)

用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了(Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the)

用Verilog HDL编写的PID程序代码，成功调试，运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)