LMS filter

一些常见的小模块，自己写的，可能不是特别好，仅供参考，主要是分频器、计数器和数码管的显示

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

关于两种实现pwm的方法 基于51单片机设计-on two methods to achieve PWM 51 microcontroller-based design

迫零-串行干扰删除检测的程序，包括16QAM和QPSK(Zero forcing- Interference Cancellation detection procedures, including 16QAM and QPSK)

说明：  All AMBA bus protocols - AXI3, AXI4, AXI4-Lite, ACE, AHB

说明：  该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)

Verilog，编写的udp收发程序，开发环境xilinx(Verilog, written UDP transceiver)

VERILOG语言速查手册,与VHDL齐名的另外一硬件描述语言(verilog language manuals, and the other enjoying VHDL hardware description language 1)

两篇中文论文，详细叙述了Farrow滤波器的设计方式和理论基础，非常实用！(Two Chinese papers, described in detail Farrow filter design methods and theoretical foundation, very useful!)

实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)