xapp265

  High-Speed Data Serialization and Deserialization(840 Mb/s LVDS) for xilinx fpga

7to1
7to1\basic_design
7to1\basic_design\verilog
7to1\basic_design\verilog\constraints
7to1\basic_design\verilog\design_files
7to1\basic_design\verilog\simulation
7to1\basic_design\vhdl
7to1\basic_design\vhdl\constraints
7to1\basic_design\vhdl\design_files
7to1\basic_design\vhdl\simulation
7to1\demo_board
7to1\demo_board\verilog
7to1\demo_board\verilog\constraints
7to1\demo_board\verilog\design_files
7to1\demo_board\verilog\simulation
7to1\demo_board\vhdl
7to1\demo_board\vhdl\constraints
7to1\demo_board\vhdl\design_files
7to1\demo_board\vhdl\simulation
8to1
8to1\basic_design_16bit
8to1\basic_design_16bit\example_ucf
8to1\basic_design_16bit\verilog
8to1\basic_design_16bit\verilog\2v1000_ucf_synpl_leo
8to1\basic_design_16bit\verilog\design_files
8to1\basic_design_16bit\verilog\simulation
8to1\basic_design_16bit\vhdl
8to1\basic_design_16bit\vhdl\2v1000_ucf_fpgax_xst
8to1\basic_design_16bit\vhdl\2v1000_ucf_synpl_leo
8to1\basic_design_16bit\vhdl\design_files
8to1\basic_design_16bit\vhdl\simulation
8to1\basic_design_20bit
8to1\basic_design_20bit\example_ucf
8to1\basic_design_20bit\verilog
8to1\basic_design_20bit\verilog\2v1000_ucf_synpl_leo
8to1\basic_design_20bit\verilog\design_files
8to1\basic_design_20bit\verilog\simulation
8to1\basic_design_20bit\vhdl
8to1\basic_design_20bit\vhdl\2v1000_ucf_fpgax_xst
8to1\basic_design_20bit\vhdl\2v1000_ucf_synpl_leo
8to1\basic_design_20bit\vhdl\design_files
8to1\basic_design_20bit\vhdl\simulation
8to1\basic_design_4bit
8to1\basic_design_4bit\example_ucf
8to1\basic_design_4bit\verilog
8to1\basic_design_4bit\verilog\design_files
8to1\basic_design_4bit\verilog\simulation
8to1\basic_design_4bit\verilog\ucf_synpl_leo
8to1\basic_design_4bit\vhdl
8to1\basic_design_4bit\vhdl\design_files
8to1\basic_design_4bit\vhdl\simulation
8to1\basic_design_4bit\vhdl\ucf_fpgax_xst
8to1\basic_design_4bit\vhdl\ucf_synpl_leo
8to1\demo_board
8to1\demo_board\verilog
8to1\demo_board\verilog\design_files
8to1\demo_board\verilog\simulation
8to1\demo_board\verilog\ucf_fpgax_xst
8to1\demo_board\verilog\ucf_synpl_leo
8to1\demo_board\vhdl
8to1\demo_board\vhdl\design_files
8to1\demo_board\vhdl\simulation
8to1\demo_board\vhdl\ucf_fpgax_xst
8to1\demo_board\vhdl\ucf_synpl_leo
xapp265
xapp265\7to1
xapp265\7to1\basic_design
xapp265\7to1\basic_design\README.TXT
xapp265\7to1\basic_design\verilog
xapp265\7to1\basic_design\verilog\constraints
xapp265\7to1\basic_design\verilog\constraints\top4_2v1000_fg456.ucf
xapp265\7to1\basic_design\verilog\constraints\top8_2v1000_fg456.ucf
xapp265\7to1\basic_design\verilog\design_files
xapp265\7to1\basic_design\verilog\design_files\m2_1p.v
xapp265\7to1\basic_design\verilog\design_files\mux2_1.v
xapp265\7to1\basic_design\verilog\design_files\serdes_4b_1to7.v
xapp265\7to1\basic_design\verilog\design_files\serdes_4b_1to7_wrapper.v
xapp265\7to1\basic_design\verilog\design_files\serdes_4b_1to7_wrapper_286.v
xapp265\7to1\basic_design\verilog\design_files\serdes_4b_7to1.v
xapp265\7to1\basic_design\verilog\design_files\serdes_4b_7to1_wrapper.v
xapp265\7to1\basic_design\verilog\design_files\serdes_4b_7to1_wrapper_285.v
xapp265\7to1\basic_design\verilog\design_files\serdes_8b_1to7_wrapper.v
xapp265\7to1\basic_design\verilog\design_files\serdes_8b_1to7_wrapper_484.v
xapp265\7to1\basic_design\verilog\design_files\serdes_8b_7to1_wrapper.v
xapp265\7to1\basic_design\verilog\design_files\serdes_8b_7to1_wrapper_483.v
xapp265\7to1\basic_design\verilog\design_files\top4.v
xapp265\7to1\basic_design\verilog\design_files\top8.v
xapp265\7to1\basic_design\verilog\simulation
xapp265\7to1\basic_design\verilog\simulation\tbtop4u.v
xapp265\7to1\basic_design\verilog\simulation\tbtop8u.v
xapp265\7to1\basic_design\verilog\simulation\TOP4U.DO
xapp265\7to1\basic_design\verilog\simulation\TOP8U.DO
xapp265\7to1\basic_design\vhdl
xapp265\7to1\basic_design\vhdl\constraints
xapp265\7to1\basic_design\vhdl\constraints\top4_2v1000_fg456.ucf
xapp265\7to1\basic_design\vhdl\constraints\top8_2v1000_fg456.ucf
xapp265\7to1\basic_design\vhdl\design_files
xapp265\7to1\basic_design\vhdl\design_files\m2_1p.vhd
xapp265\7to1\basic_design\vhdl\design_files\mux2_1.vhd
xapp265\7to1\basic_design\vhdl\design_files\serdes_4b_1to7.vhd