主要是步进电机的驱动源，用Verilog VHDL开发，个人取向…

彩色空间转换，RGB和YUV互转的matlab源码(RGB converting to YUV, YUV converting to RGB, Matlab source code)

basic verilog for students

基于FPGA的PWM控制器设计，包含ADC0820模块，按键扫描，PID，PWM控制器等模块，VHDL语言完成，已仿真通过(PWM controller design based on FPGA, including ADC0820 module, key scan, PID, PWM controllers and other modules, VHDL language completed, through simulation)

本文介绍了汉明编码与译码通过FPGA器件来实现，介绍了使用VHDL语言编程的基本算法！-This article describes the Hamming encoding and decoding through the FPGA device to implement, introduced the use of VHDL programming language is the basic algorithm!

基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.

在quartus平台下，并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)

说明：  VHDL语言的有限状态机法控制8位/12位自动转换通道模数转换器AD7938(VHDL, FSM method to control 8-bit/12-bit ADC AD7938 auto-conversion channel)

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

cycloneIII_3c120_dev_power_demo atlera公司官方例程(cycloneIII_3c120_dev_power_demo atlera company official routines)

初学cpu结构的很好的verilog代码的示例，适合初学者(novice cpu structure of the good verilog code examples for beginners)