Verilog prepared practical multi

uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps

数字平律己的设计非常实用 黄永显示早设计大方ijasd-The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd

关于Digilent Atlys Spartan-6 FPGA development board　audio ac97的讲解及具体应用的源码(Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code)

msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures

用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.

显示频率测量，外接24MHz晶振，显示数据为三位，分四个档来测量-show frequency measurement, external 24MHz crystal oscillator, the data show that three, four hours to measure stalls

用VHDL语言写的代码 包括全局的输入时钟缓冲器来去抖动，块RAM模块65536*10，读数据，写数据，空标志信号的产生，满标志信号的产生，读写使能信号的产生七个模块！对各位有帮助噢！

输入的8X8图像数据块包括在范围从0到255的整数。在DCT计算的平均值减去128从输入数据中最小的输入数据块的冗余。核心可以计算输入数据的范围128到127以及–。然后，平均值128不减。在DCT的计算，数据可以减少到重要的信息集中到少数的DCT结果，留下剩余的系数等于零。这意味着图像的能量集中 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

说明：  实现简单的硬件加法器、除法器，实现源码文中注释(Realize simple hardware adder and divider, realize source code)

verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )