有关FIFO的代码

基于XIlinx ISE，用Verilog语言实现3分频电路，适合初学者(Based XIlinx ISE, Verilog language using the frequency dividing circuit 3, suitable for beginners)

网络通信中的MII接口 通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用 同时包含84转换(The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the same time contains 84 conversion)

说明：  LIUSHUIDENG VHDLYUYAN XIADE SHUIDENG(LEDWATER I WRITER IT MYSILF.IT'S EASY ! YOU CAN WRITER IT,TOO)

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.

VIVADO 从此开始,详细讲解了vivado,FPGA开发工具的使用，对于初学者学习VIVADO工具很有用。(VIVADO from now on, explained in detail the use of vivado, FPGA development tools, for beginners to learn VIVADO tools very useful.)

数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;

本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn

用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.

一个用于数字解调的应用程序，主要用于数字接收机的应用方面-A demodulator for digital applications, mainly for the application of digital receiver

用Verilog语言实现QPSK调制，QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。 (Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)