The design of digital self

用verilog hdl写的Norflash控制器，可实现单字节读写，扇区擦除。(Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.)

rc6 algorithm designed based on verilog and is verified

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。(This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.)

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)

轴系测试程序，多通道输入输出，实现时域、频域、轴心轨迹、瀑布图等功能。(Shafting test program, multi-channel input and output, to achieve time domain, frequency domain, orbit, waterfall and other functions.)

主要用来介绍如何编写高质量的verilog程序的(Is mainly used to describes how to write high-quality verilog programs)

sdram 代码在最后要强调的是，本专题以技术为主，由于篇幅的原因，不可能从太浅的方面入手，所以仍需要有一定的技术基础作保证，而对内存感兴趣的读者则绝不容错过，这也许是您最好的纠正错误认识的机会！

ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface )

SDIO slave, written in verilog, does not support SPI mode.