UART串口传输的Verilog RTL

一个用VHDL编写的跑马灯程序和60进制计数器的程序，一个是自己设计的一个是老师要求，都在实验箱上验证成功，希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.

这是一个JPEG的编解码的VHDL程序代码-This is a JPEG codec the VHDL code

说明：  一种能简单的实现I2C通讯的代码，对于主机和从机之间的通讯讲解的很清楚。(A Code for I2C Communication)

用CPLD驱动数码管，实现从0000计到9999，数码管是用动态显示，程序用VERILOG完成的-CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG

说明：  在quartus上运行16QAM仿真，实现在modelsim上的波形仿真(Running 16QAM simulation on quartus)

在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.

交通灯控制器，verilog，可控制两个方向各四盏灯的亮灭，并具有时间显示(traffic light controllor，by verilog)

主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图(Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for quartusII 7.0, for a project, can be downloaded directly to the FPGA, including circuit diagrams)

此为数字逻辑书上的答案，应该很多同学都需要吧，关于数字逻辑(This is the answer books, digital logic, it should be a lot of students need it, on the digital logic)

UART串口的verilog源代码，完全正确...........(UART serial Verilog source code, completely correct ...........)