用VHDL语言设计四位全加器，有低位进位和高位进位。

vhdl code for carry lookahead addder

例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)

说明：  用VHDL语言设计一个校验器，用for loop实现8位数据的偶校验，(With a for loop to achieve 8-bit data parity)

用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)

说明：  HDMI做为视频输出输入接口已经广泛使用很长时间，主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验，来练习视频的时序和视频颜色的表示，为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)

this ebook for electronics hobbiest. VHDL for Beginners

alter FPGA，包含sdram的nios系统开发实验完整工程文件-nios develop based nios IDE6.0，system involved an sdram

pc104接口的verilog代码，仅供参考-pc104 verilog interface code for reference purposes only

vc707 board getting started guide

adding custom ip EDK