用VHDL语言设计四位全加器，有低位进位和高位进位。

SPI串口的内核实现（vhdl）,可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.

matlab file for image contrast..

n bit generic shift registers

4 级流水方式的8 位全加器。。。。。。(Way flow of 4 full adder 8. . . . . .)

EDA的交通信号灯的控制系统的程序,设计一个交通信号灯控制器，由一条主干道和一条支干道汇合成十字路口，在每个入口处设置红、绿、黄三色信号灯，红灯亮禁止通行，绿灯亮允许通行，黄灯亮则给行驶中的车辆有时间停在禁行线外。(EDA traffic lights control system procedures)

verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10

实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.

说明：  this code works with spi and uart interfaces.

verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language