用VHDL语言设计四位全加器，有低位进位和高位进位。

DSP与FPGA时序接口模块，已经经过测试，保证读写稳定(The Interface of DSP to FPGA)

Efficient CIC filter Implementation using VHDL

very much verilog code for the beginner

A quick and simple Spartan 3 tutorial

interruption routine for PIC16F877

VHDL code for converting BCD to Decimal

在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下 变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所 采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字 下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了 数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)

EDA常用双LED显示译码程序，将四位二进制数译码为七位对应于LED7位输入的高低电平信号-EDA common dual LED display decoding procedure will be four binary decoding for seven LED7 spaces corresponding to the input signal circuits

用vhdl语言生成锯齿波，数据可自行改变(Sawtooth wave with vhdl language generation, the data can change by itself)

从FIFO到到RS232的实现，用于接收和缓存数据(TripAdvisor RS232 FIFO implementation for receiving data and cache)