dct idct 编码

TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)

驱动0.96寸的oled显示数字和字母，(Drive 0.96 inch OLED to display numbers and letters.)

基于CPLD的交通信号灯的实现，使用VHDL语言，使用不同颜色的二极管分别代表红黄绿三种信号灯。在数码管上可以分别显示倒计时。

带有电网电压反馈的单相PWM整流器反馈，输出的波形很好，适合初学者学习观摩(With power grid voltage feedback single-phase PWM rectifier feedback, the output waveform is very good, suitable for beginners learning view )

基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....

Fun little FPGA that plays a portion of Habanera

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF

半整数分频器的实现（verilog），本文以6.5分频为例！很实用的！-fen pin qi

说明：  本书纸版由机械工业出版社于2014年出版，张强编著，电子版由华章分社（北京华章图文信息有限公司）全球范围内制作与发行(The book was published in paperback by China machine press in 2014, and edited by zhang qiang. The electronic version was produced and distributed worldwide by huazhang branch (Beijing huazhang graphic information co., LTD.))

1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES