dct idct 编码

一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows

青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA，自己写的AVALON总线IP核，供大家参考-err

Building the CPU datapath

宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

用可编程逻辑器件实现PWM波形即PWM波形发生器-Using programmable logic devices that realize PWM waveform PWM Waveform Generator

使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)

原理图和程序，都已经调试好了！可以直接使用！

说明：  This paper analyzes the cryptography scheme of the Trust Platform Model(TPM). The focus of the discussion would be the comparison of elliptic curve cryptography and the nowadays widely used 2048-bit RSA in evaluating which would be better suited to be used on TPM. A TPM implementation scheme based on ECC is proposed, which includes encryption and decryption schemes, signature and verification scheme, key agreement scheme. Corresponding examples of TPM commands would also be given.

Verilog HDL 高级数字设计源码 _chapter4(Advanced Digital Design Verilog HDL source _chapter4)