位同步例程源代码,FPGA应用领域，Verilog

HDMI做为视频输出输入接口已经广泛使用很长时间，主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验，来练习视频的时序和视频颜色的表示，为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)

sdi音频嵌入及解嵌代码,代码使用Verilog HDL语言(SDI audio embedding and decoding code, the code using Verilog HDL language)

vhdl,序列信号发生器，发出11101010，可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of

并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through)-- The code can now achieve a single byte of Transceivers

DDS基本原理，详细讲述了DDS基本原理及设计技巧(DDS Basic principle)

verilog源代码，实现两种方法的模3运算。(verilog source code，to implement the calculation of mod-3 by two means.)

A Dec example written in VHDL.

VHDL Vendingmachine source

Program to implement convolution through VHDL-Program to implement convolution through VHDL...

VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)