位同步例程源代码,FPGA应用领域，Verilog

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

直接序列扩频通信的Verilog仿真代码，在Quartus II中实现。(Direct sequence spread spectrum communication Verilog simulation code, implemented in Quartus II.)

说明：  一个8位RiSC单片机的VHDL代码， 具有很好的参考价值。(an eight RiSC SCM VHDL code, is a good reference value.)

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

Implementation of Image Processing Algorithms in FPGA Hardware.

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)

字长可以简单调整，即可实现任意字长UART通讯(The word length can be simply adjusted to achieve any word length UART communication.)

说明：  用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)