位同步例程源代码,FPGA应用领域，Verilog

PLL中的TDC和DCO代码,是TI公司团队的，相当经典的代码，非常不错(the code of TDC and DCO)

此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of the generation of the signal of sin and the design of fir filter and the ari)

Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.

verilog da0832 cpldfpga control-verilog da0832 cpldfpga control

spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

本实验主要是在FPGA上实现FIR数字滤波器的功能，不仅有工程文件，还具有论文资料。(This experiment mainly realizes the function of FIR digital filter on FPGA, not only has the engineering document, but also has the thesis information.)

基于研华采集卡的FIFO双缓存区高速数据采集(FIFO DAQ)

FIR滤波器的VHDL语言实现(The implement of FIR Filter based on VHDL)

C6000系列之6701开发板相关文件及说明(C6000 Series of 6701 development board-related documents and notes)