VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)

基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)

使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock

FPGA板上的锁存器PLL控制代码（verilog代码）(FPGA board latch the PLL control code (Verilog code))

cpld 控制 8-32M sdram 控制器 maxII epm570实现。-CPLD control 8-32M sdram controller maxII epm570 realize.

Verilog语言下QAM调制的DDS实现(The QAM Modulation DDS achieve)

自己写的7人表决器的verilog程序，实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)

说明：  基于FPGA，用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)

verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)

特大好消息，这是LED全彩控制卡的FPGA的源程序，做LED开发的，绝对有很好的价值(Big good news, this is full-color LED control card FPGA of the source, do LED development, the absolute value of good)

程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the