VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)

不错的介绍verilog的电子文档，对于入门级的新手有不错的参考价值-A good introduction to verilog electronic documents, for the novice there is a good entry-level reference value

library of protues aaaaaaaa

VHDL Coding style guide

Synopsys® Timing Constraints and Optimization User Guide

鼎lpc1788尚开发板的vga的显示，1024x768(lpc1788board,lcd to vga display,1024x768)

说明：  通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)