cpld 控制 8

ASK,FSK,PSK,DPSK调制解调的详细仿真代码(ASK, FSK, PSK, DPSK modulation and demodulation detailed simulation code)

一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.

在FPGA开发板上用VHDL语言实现了贪吃蛇游戏，开发软件为quartus 2.这是详细的实验报告，包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)

Vending Machine simulation using Moore sequence

modelsim快速入门教程，附带文中范例源代码。-ModelSim Quick Start Guide, incidental text in an example of source code.

小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)

VESA CVT视频参数计算器，输入分辨率和刷新率即可得到需要参数。(VGA Timing Calculator)

FPGA的存储器代码的VHDL,verilog描述及测试代码-FPGA memory code VHDL, verilog description and test code

基于quartus 的一些程序 都是verilog 还是比较有用的 -Based on some of the procedures Quartus Verilog are still quite useful

1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES