I2C控制器源代码，Verilog HDL语言，可以直接调用

此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)

4位ALU,有两个4位输入，4位输出实现逻辑运算和算术运算，逻辑与或非，加1，减1等等功能(4 ALU, logical and arithmetic operations)

这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing

基于FPGA的16*16点阵中文LED显示，另带有几个简单的中文汉字的点阵数据。(FPGA-based 16* 16 dot matrix Chinese LED display, and the other with a few simple lattice data Chinese characters.)

DDS基本原理，详细讲述了DDS基本原理及设计技巧(DDS Basic principle)

含移动储能的分布式电能优化调度，模型的处理与改进(Processing and improvement of distributed power optimization scheduling with mobile energy storage)

VHDL语言写的频率计的程序，内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report

说明：  基于VHDL的多路抢答器，用LCD12864进行显示(Multiplex answering device based on VHDL is displayed with LCD12864)

任意奇数分频，只要修改N即可实现 可验证-Arbitrary odd-numbered sub-frequency, as long as the modified N can realize verifiable

Advanced FPGA Design Architecture, Implementation, and Optimization