I2C控制器源代码，Verilog HDL语言，可以直接调用

FIR数字滤波器程序，采用vhdl编写，可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit

自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)

ddr3使用教学(DDR3 using teaching)

基于verilog语言的数据选择器，包括数据选择器的测试模块 (verilog language based on the data selector, including data selection for the test module)

驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)

说明：  用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )

adding custom ip EDK

VHDL学习手册-VHDL study manual

《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.