在SOPC Builder的UART IP核接口

计算机组成原理课程设计代码，课程设计，计组(Computer organization principle curriculum design code, curriculum design, group calculation)

verilog，4、5分频器，5分频器占空比3：2-Verilog, 4,5 dividers, five dividers ratio of 3:2

基于FPGA设计ADC0809采样控制器原代码-FPGA-based design ADC0809 Sampling Controller source

VHDL implementation using mouse and monitor

说明：  基于数据通路和控制器的高校简单PPM设计(PPM design based on datapath and controller)

135个经典VerilogHDL源码和说明文档，入门的好资料-135 Classic VerilogHDL source and documentation, a good data entry

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.

注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)

说明：  fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

An odd parity checker as an FSM using VHDL