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shumaguandongtai
VHDL的动态扫描显示六个数码管,包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)
- 2012-11-26 14:40:42下载
- 积分:1
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RecentProjectCleaner
vs自定义插件开发,带卸载功能,经测试完全可用,分享给大家,可以学习!(vs custom plug-in development, with the uninstall feature, has been tested and is fully available for everyone to share, you can learn!)
- 2014-12-24 11:35:54下载
- 积分:1
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lcd-ip-core
LCD 驱动的IPCORE,可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)
- 2011-02-15 11:34:38下载
- 积分:1
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tlm
tlm基本框架,生产消费模型例子
tlm基本框架,生产消费模型例子
tlm基本框架,生产消费模型例子(tlm basic framework, examples of production and consumption model)
- 2010-01-27 17:31:47下载
- 积分:1
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ROM模块,功能在于,是创建一个简易的rom模块
ROM模块,功能在于,是创建一个简易的rom模块-rom
- 2022-03-31 16:48:46下载
- 积分:1
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青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA,自己写的AVALON总线IP核,供大家参考...
青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA,自己写的AVALON总线IP核,供大家参考-err
- 2022-04-07 09:35:28下载
- 积分:1
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基于FPGA的实现小数倍分频代码,广泛应用于数字通信中。
基于FPGA的实现小数倍分频代码,广泛应用于数字通信中。-FPGA-based implementation of a small multiple of sub-frequency code, widely used in digital communications.
- 2022-04-19 03:39:18下载
- 积分:1
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官方的RS232例程详细Altera非常实用
altera 官方rs232例程 很详细很实用-official rs232 routines in great detail altera very practical
- 2023-04-15 09:15:03下载
- 积分:1
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VHDL实例这是我下载到的最好的VHDL实例,看完这些实例,可以使你有一个长足的进展...
VHDL实例这是我下载到的最好的VHDL实例,看完这些实例,可以使你有一个长足的进展-VHDL example
- 2022-08-10 14:33:29下载
- 积分:1
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32bit_multiply
包含32为乘法器的设计,用verilog语言实现,包括booth编码的实现,booth乘法器的实现,3_2压缩器的实现,4_2压缩器的实现,华伦斯树的实现,以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)
- 2015-01-18 21:20:48下载
- 积分:1