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leading-zero
对于32位寄存器前导零个数的计数,一个简单的程序(32 registers a leading zero number of counts, a simple procedure)
- 2012-06-05 16:41:11下载
- 积分:1
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VerilogHDL_advanced_digital_design_code_Ch4
Verilog HDL 高级数字设计源码 _chapter4(Advanced Digital Design Verilog HDL source _chapter4)
- 2007-11-27 10:10:43下载
- 积分:1
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DisplayPort Link training optimization
说明: 介绍了Displayport规格中lind training的背景研究,设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining
the signal integrity becomes increasingly more difficult. For many of todays
commonly used video interfaces, there are devices that can be used to assist in this
matter. However, the use of such a device is only partially documented in the DisplayPort
specification for the receiving image device, which means that the receiving
side of the video link is free to choose its own implementation. This report presents,
together with background research and design decisions, a suggestion for such an
implementation. This implementation would need to be compatible towards a wide
range of possible video Source devices and DisplayPort cables.)
- 2021-01-11 16:48:49下载
- 积分:1
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对NC Verilog的基本介绍,详细的图解,非常适合初学者使用,一个word文档和一个pdf文档...
对NC Verilog的基本介绍,详细的图解,非常适合初学者使用,一个word文档和一个pdf文档-NC Verilog on the basic introduction, detailed diagrams, very suitable for beginners to use, a word document and a pdf document
- 2022-08-12 19:52:59下载
- 积分:1
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Interpolation-in-Digital-Modems
Farrow 滤波器设计经典文章,作者是:FM.Gardner,farrow滤波器设计的始祖,经典值得推荐!(两篇文章)(Farrow filter design classic article, the author is: FM.Gardner, farrow filter design ancestor, classic worth recommending! (Two articles))
- 2013-11-15 17:57:22下载
- 积分:1
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QAM发生仿真
在Qaurtus环境下用Verilog输入实现64QAM信号的发生,用MATLAB协助验证,观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)
- 2021-03-02 23:39:33下载
- 积分:1
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XadcMicroblaze-master
说明: 用zynq实现片内的数模转换,基于最新的zynq平台(zynq xadc on FPGA arm)
- 2020-06-21 12:00:02下载
- 积分:1
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verilogCRC32
32位bit输入的CRC32校验,verilog的代码,以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)
- 2012-03-07 10:22:58下载
- 积分:1
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VHDL-SUBWAY
基于QuartusII环境下的地铁自动售票系统(Subway auto ticketing system based on QuartusII)
- 2011-04-20 09:35:24下载
- 积分:1
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fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过...
fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
- 2023-07-19 00:45:03下载
- 积分:1