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USART
基于USART的ARM与FPGA通信实验(Based on the ARM and FPGA communication experiment of USART
)
- 2017-04-15 16:58:30下载
- 积分:1
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VHDL实现交通灯
VHDL实现交通灯-VHDL traffic lights
- 2022-04-07 20:09:13下载
- 积分:1
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用于FPGA的反量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA used to quantify anti-HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-04-08 04:33:51下载
- 积分:1
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本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设
计,包括偶数分频、非 50%占空比和 50%占空比的奇数分频、半整数
(N+0...
本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设
计,包括偶数分频、非 50%占空比和 50%占空比的奇数分频、半整数
(N+0.5)分频、小数分频、分数分频以及积分分频。所有实现均可
通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合,形成可使
用的电路,并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
- 2022-08-24 20:51:04下载
- 积分:1
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Basic-system-of-nexys3
the basic system of nexys3(soft core)
- 2012-09-21 23:41:14下载
- 积分:1
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这是用VHDL实现的8位加法器,对新手有点帮助。
这是用VHDL实现的8位加法器,对新手有点帮助。-This is achieved using VHDL adder 8, a little help to novices.
- 2022-07-20 21:54:41下载
- 积分:1
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基于NiosⅡ的2 de2_tvproject
本演示使用VGA输出和DVD播放器播放视频和音频输入
- 2022-01-26 03:44:01下载
- 积分:1
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WigglerJTAG
Wiggler Clone .JTAG Schematic and PCB in Altium Designer Format
- 2009-07-17 19:27:27下载
- 积分:1
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AD5791_spi
该代码为VHDL语言描述的AD579 SPI通讯程序,包括一些代码注解。(Thisis a SPI communication promgram of AD5791 designed with VHDL which compared with some discreption.)
- 2021-04-20 14:28:50下载
- 积分:1
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Verilog的150个经典设计实例
Verilog经典实例.包括洗衣机红路灯、兹自动方麦基、等式子可用(Classic examples of Verilog. Including red street lights for washing machines, ZAM, equation availability)
- 2021-03-17 16:49:20下载
- 积分:1