可编程逻辑器件cpld与单片机双向通信的源程序

说明：  这是一款由晶振产生的脉冲控制的数字钟，可以从00:00:00到23:59:59之间进行计时。(this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.)

this code for integrator for 8 bit signal

VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)

vga 测试代码，可以显示任意彩条，棋盘，花纹(VGA test code, can display any color bar, chess board, decorative pattern )

costas载波恢复算法 锁相环路，注释很清楚(costas carrier recovery algorithm PLL)

verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)

Convolutional neural network code for fpga

circuit design with VHDL e-book MIT Press....

VHDL参考手册，从事FPGA的好帮手，FPGA学院的终身伴侣！-VHDL Reference Manual, in FPGA a good helper, FPGA college life companion!

AES算法在FPGA上的实现，对AES算法所用的器件资源进行了总结(AES on FPGA the Fastest to the Smallest)