verilog HDL 写的LMS滤波器

simple code based on verilog shifter , cla ,clg , ALU , PC

FCFS (First Come First Served) with Database

基本功能的cpu，自定义内存内容~了解CPU运作原理~(design of cpu,VHDL environment~)

Verilog code for RS-(255,239) encoder.

Control with DAC conversion

Synthetic Aperture Radar (SAR) imaging simulation target, Using wavelet denoising thought, LCMV optimization design array signal processing.

这是OFDM调制matlab的程序，中间详细描述了调制的过程，希望对大家有用。(This is the OFDM modulation matlab procedures, a detailed description of the intermediate modulation process, I hope useful.)

verilog ADPLL file with testbench.v

采用vhdl代码描述自适应滤波器，具有很好的可参考性，和实用性(Vhdl code to describe the use of adaptive filter, can be found with a good nature and usefulness of)

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been