verilog HDL 写的LMS滤波器

这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]

usb控制器，有VHDL实现的，还有C++的源码，可以编译-usb controller, there is the realization of VHDL, as well as C++ source code can be compiled

万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

说明：  this code works with spi and uart interfaces.

一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference

它是一个基于verilog的数字时钟，显示时-分-秒，它可以手动输入，并为时、分和秒分配3个开关第二，它数字时钟频率是实时设置的。我自己用逻辑开发的。。。

使用FPGA控制永磁同步电机的代码，实现对永磁同步电机的控制功能。(Motor control by using FPGA)

说明：  verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.