对与单片机常用的功能看门狗，本程序用vhdl硬件语言实现次功能。...

Use full for knowing board details while making projects on FPGA and matlab simulations

单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件-Voltage pulse control of a project- including VHDL source code and compile the relevant documents after

快速傅立叶变换(FFT)作为时域和频域转换的基本运算，是数字谱分析的必要前提。传统的FFT使用软件或DSP实现，高速处理时实时性较难满足。FPGA是直接由硬件实现的，其内部结构规则简单，通常可以容纳很多相同的运算单元，因此FPGA在作指定运算时，速度会远远高于通用的DSP芯片。FFT运算结构相对比较简单和固定，适于用FPGA进行硬件实现，并且能兼顾速度及灵活性。本文介绍了一种通用的可以在FPGA上实现128点FFT变换的方法。设计复数乘法器为核心设计了FFT算法中的基-2蝶形运算单元，溢出控制单元和地址与逻辑控制模块等其它模块,并以这些模块和FPGA内部的双口RAM为基础组成了基-2FFT算法模块。 

verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)

Documentation Of Digital Electronic Systems With VHDL from US DOD.

利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图，回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)

CORDIC(Coordinate Rotation Digital Computer)算法即坐标旋转数字计算方法。 CORDIC算法,能够通过平移和累加快速实现基础的数学函数,包括三角函数,开方,指数,对数,平方根等函数。(CORDIC (Coordinate Rotation Digital Computer) algorithm for the coordinate rotation digital calculation. CORDIC algorithm can be achieved through the rapid translation and accumulation based on mathematical functions, including trigonometric, square root, exponential, logarithmic, square root and other functions.)

用FPGA实现的VGA/LCD显示的相关知识,包含了程序的主要结构和主要功能模块的实现过程-Using FPGA to achieve the VGA/LCD display relevant knowledge, including the procedures for the main structure and main function modules of the realization process

Verilog实现 spi接口的FPGA实现 通过仿真，修改后即可应用-Verilog realize spi interface FPGA to achieve through the simulation, the application can be modified